Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97)
نویسندگان
چکیده
In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works of the literature for F397 . We also propose new formulas for multiplication in F36·97 . These new formulas reduce the number of F397 multiplications from 18 to 15. The finite fields F397 and F36·97 are important fields for pairing based cryptography.
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